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ADN8810 SPI timing

Question asked by IanWillats on Feb 11, 2014
Latest reply on Feb 20, 2014 by IanWillats

Hello,

 

I have some questions about the SPI timing on the ADN8810 laser current source (hope this is the right place to ask, please let me know if not).

 

The background to this is that I would like to run the device at a high sample rate using back-to-back SPI transactions.  That is, the SPI should be clocked continuously and every clock cycle should transfer one bit of the 16-bit address/data word.

 

Based on the description of the serial data interface I am assuming that the /CS input is asynchronous (not sampled by SCLK) and  needs to be pulsed high for a minimum of 30 ns some time during the last SCLK cycle of each transaction (after the rising edge of SCLK on which D0 is sampled).  That being the case it looks possible to run back-to-back cycles if the /CS signal remains low except for a short high pulse during the last data bit of each 16-bit transaction.


  • Is this mode of operation feasible?  If not, what is the minimum required number of SCLK rising edges with /CS high?
  • Is the purpose of t5 (/CS High to SCLK High Setup) to define how early /CS must be negated to guarantee that a rising edge of SCLK does NOT clock data into the shift register?

 

Thanks in advance for your help.

 

Ian

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