I am working with EVAL-ADF4351EB1Z in order to validate this PLL+VCO IC for our future receiver design. In that case, I am driving the evaluation board with external 10MHz reference, because this will be our reference input in the definitive design. I need to synthesize frequencies between 300-500 MHz and I have requirements such as phase noise less than -107dBc/Hz@10KHz, ACP@offset_25Khz < -70dBc and spurs less than -82dBc in RF output.
Now, I am playing with a Loop filter bandwidths as narrow as I can (1KHz) because I have seen that using the 35KHz of the evaluation board loop filter I can´t achieve spurs below -82dBc.
My question is the following: Is it possible to synthesize frequencies with ADF4351 fulfilling all my specs? I have simulated several configurations in ADIsimPLL but I have not achieve the expected results.
If it was possible, what kind of configuration should I set in ADF435x SW ?
Thanks in advance,