(First post, please go easy on me...)
I have some questions about the SPI timing on the AD5621 DAC. The background to this is that I would like to run the device at a high sample rate using back-to-back SPI transactions. That is, the SPI should be clocked continuously and every clock cycle should transfer one bit of data (bearing in mind that only 12 of the 16 are actually part of the DAC code). The timing information and description of operation of the serial interface in the data sheet seems to suggest that should be possible if the /SYNC signal remained low except for a short high pulse during the last data bit of each 16-bit transaction.
Which leads to the following questions:
- Is this possible? Or must there be one (or more) SCLK falling edges with /SYNC high?
- What is the minimum high time for /SYNC? The timing specification (t8) says 20 ns, but the description of the serial interface says 33 ns which seems to be a direct contradiction.
- Exactly what is meant by t9, described as "/SYNC rising edge to next SCLK falling edge ignored"?
Thanks in advance for your help.