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AD9643 PCORE for AD-FMCOMMS1-EBZ Questions

Question asked by kcfarleysw on Feb 10, 2014
Latest reply on Feb 13, 2014 by rejeesh

Engineer Zone:

 

I have the following questions about AD9643 PCORE:

 

1) What is the rate of adc_clk in ax_ad9643.v ? Is it 250 Mhz?

2) What is the rate of the dma_clk ? Is it 125 Mhz?

3) What is the format of data from axi_ad9643_if? Is it two samples per adc clock[250 Mhz]?

4) What is the format of data going into dma_core?

5) Please explain following code: lines 280 to 302 of axi_ad9643.v

 

always@(posedge adc_clk) begin

     adc_data_cnt <= adc_data_cnt + 1'b1;

     case ({adc_enabl_b_s, adc_enable_a_s})

         ....

         2'b11: begin //Both I and Q

             adc_valid <= ....

             adc_data <= {adc_channel_data_b_s, adc_channel_data_a_s, adc_data[63:32]};

         end

 

         I don't understand what concatenating adc_data[63:32] into adc_data is accomplishing?

         adc_data[63:32] isn't being set any where else? Is it just stuffing zeros to lower 32 bits?

 

6) Please explain axi_ad9643_if.v and ddr[I assume double data rate] operation. I am a little confused.

    Is it getting two samples every clock at 250Mhz? How is it demuxing into a stream that the dma can handle?

5) Please explaing how the dma_core operates. What is the dma_start,dma_stream,dma_count used for? How is that different from

the dma data?

 

Thanks,
Ken Farley

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