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Wrong HDMI clock frequency from axi_clkgen

Question asked by StevenB on Feb 10, 2014
Latest reply on Feb 10, 2014 by StevenB

I'm attempting to combine the zc702/ADV7511 reference design with another design, and have mostly gotten it to work, except that the HDMI clock frequency is off.  The output from /sys/kernel/debug/clk/clk_summary is

          fclk2_mux             1           1            999999990
             fclk2_div0         1           1            199999998
                fclk2_div1      1           1            199999998
                   fclk2        2           2            199999998
                      axi-clkgen 1           1            33333333 

 

The problem seemed suspiciously similar to this thread (http://ez.analog.com/message/125266#125266), so I added some printk's to the code.  The patch in the linked thread didn't work for me.  The system is connected to a 1080p monitor, and the output is below (registers and values are in hex; rates are decimal).

 

axi_clkgen_v2_mmcm_read - reg: 8  val: 10c3
axi_clkgen_v2_mmcm_read - reg: 16  val: 10c3
axi_clkgen_v2_mmcm_read - reg: 14  val: 10c3
axi_clkgen_recalc_rate - tmp: 0  parent_rate: 33333333
axi_clkgen_v2_mmcm_read - reg: 8  val: 10c3
axi_clkgen_v2_mmcm_write - reg: 8  val: c3
axi_clkgen_v2_mmcm_read - reg: 9  val: 10c3
axi_clkgen_v2_mmcm_write - reg: 9  val: 0
axi_clkgen_v2_mmcm_read - reg: 16  val: 10c3
axi_clkgen_v2_mmcm_write - reg: 16  val: 2146
axi_clkgen_v2_mmcm_read - reg: 14  val: 10c3
axi_clkgen_v2_mmcm_write - reg: 14  val: 619
axi_clkgen_v2_mmcm_read - reg: 15  val: 10c3
axi_clkgen_v2_mmcm_write - reg: 15  val: 80
axi_clkgen_v2_mmcm_read - reg: 18  val: 10c3
axi_clkgen_v2_mmcm_write - reg: 18  val: fa
axi_clkgen_v2_mmcm_read - reg: 19  val: 10c3
axi_clkgen_v2_mmcm_write - reg: 19  val: 7c01
axi_clkgen_v2_mmcm_read - reg: 1a  val: 10c3
axi_clkgen_v2_mmcm_write - reg: 1a  val: 7fe9
axi_clkgen_v2_mmcm_read - reg: 4e  val: 10c3
axi_clkgen_v2_mmcm_write - reg: 4e  val: 800
axi_clkgen_v2_mmcm_read - reg: 4f  val: 10c3
axi_clkgen_v2_mmcm_write - reg: 4f  val: 8008090
axi_clkgen_set_rate - rate: 148484847  parent_rate: 199999998
axi_clkgen_v2_mmcm_read - reg: 8  val: 10c3
axi_clkgen_v2_mmcm_read - reg: 16  val: 10c3
axi_clkgen_v2_mmcm_read - reg: 14  val: 10c3
axi_clkgen_recalc_rate - tmp: 0  parent_rate: 33333333

 

I'm currently running a kernel built from git revision b769d26, on the xcomm_zynq_new_pcore_regmap branch.

 

My device tree has the lines below for the clock generator.  The device address assigned in XPS is 0x79000000, and it is v2.00 of the IP.

        hdmi_clock: axi-clkgen@79000000 {
            compatible = "adi,axi-clkgen-2.00.a";
            reg = <0x79000000 0x10000>;
            #clock-cells = <0>;
            clocks = <&clkc 17>;
        };

 

It seems like the system is leaving out the divide-by-11/multiply-by-49 piece of the clock generator, and just dividing the input by 6.

What do I need to try next?

Thanks!

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