a question regarding the SYSCLK2 output on ADAV801.
At XIN I have a 27MHz crystal, at SYSCLK2 I need 24.576 MHz with 50% duty cycle.
Because I use PLL2 and double sample rate (48 kHz x 2), I need to write in register 0x75 the value 0x10. So I get at SYSCLK2 24.576 MHz with a duty cycle of 34% !!
If I take out the duplication (FS2 / 2), so write the value 0x00 in the register, the duty cycle is changed to 50%.
If the sample rate for PLL2 set to 44.1 kHz and switched to double (FS2) again, I also get 50% duty cycle.
I write 0x40 in the register (Actually Reserved) and get a sampling rate of 48 kHz with doubling and duty cycle 50%, Although bit 4 of 0x75 is not set (?).
However, de value 0x50 is working. Are that settings that operate safely, or is it not specified?
Is there an explanation for this behavior?