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BF609 processor core stall ( possibly anomaly 16000032 ? )

Question asked by Rudstone on Feb 10, 2014
Latest reply on Feb 19, 2014 by StuartS

I've been getting a complete processor stall in my BF609 application, when the stall has occured ( visible as all data on the RS232 port stops ), if a pause the application witht he debugger the location is always in the UARTStatusHandler routine of the supplied uart driver.  Specifcally its at the read of the UART_STAT register.

 

StatRegValue = ADI_ANOM_16000030_READ32(&pDevice->pUARTRegs->UART_STAT);

 

static uint32_t adi_anom_16000030_read32(volatile const uint32_t * mmr) {

  /* Performs a 32-bit MMR read while interrupts are disabled. */

  uint32_t imsk;

  uint32_t mmrContents;

  imsk = cli();  /* clear interrupts */

  mmrContents = *mmr;

  sti(imsk);     /* restore interrupts */

  return mmrContents;

} /* adi_anom_16000030_read32 */

 

from disassembler

 

StatRegValue = ADI_ANOM_16000030_READ32(&pDevice->pUARTRegs->UART_STAT);

R0 = [ P1 + 0x34 ] ;

R0 += 4 ;

[ FP - 36 ] = R0 ;

imsk = cli(); /* clear interrupts */

CLI R0 ;

[ FP - 4 ] = R0 ;

[ FP - 12 ] = R0 ;

mmrContents = *mmr;

P1 = [ FP - 36 ] ;

R0 = [ P1 ] ;  // stalls on this instruction

[ FP - 8 ] = R0 ;

sti(imsk); /* restore interrupts */

R0 = [ FP - 12 ] ;

[ FP + 0x10 ] = R0 ;

STI R0 ;

return mmrContents;

R0 = [ FP - 8 ] ;

 

Once stalled the SEQSTATs NSPECABT flag is set, and the application can the be unstalled by unpausing.

 

This behaviour only occures if I have Data Cache Enabled and in Write Through mode ( it does not appear to happen in Write Back ), and that the Stack is in L3 cachable memory.

 

If I move the stack to non cached L3 all appears to work fine.

 

System is CCES version 1.0.3.0 ( all updates applied )

BF609 silicon revision 1.0 running on Avnet Finboard.

Imported FreeRTOS OS

running Uart task to echo characters no other drivers required to produce the issue.

 

I believe this to be anomaly 16000032 - Core Reads of System MMRs May Cause the Core to Hang:

 

Any commets on this?

Is putting the Stack in a cachable region an issue otherwise. ( Setting the system stack to L3 in the system.svc editor puts it in a bank 2 which is defaulted to cachable ).

 

For now I will ensure the RTOS puts the stacks in uncached memory.

 

Thanks in advance.

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