Dear Analog Devices
I am having challenge in clarifying some details regarding the use of the AD9508.
My intention is to implement the clock fan-out buffer towards three ADV7180 analog video decoders. I suggest to use a 57.2727MHz (+/-25ppm) oscillator, clocking the AD9508. By dividing by two, I expect to get the 28.6363MHz output to the ADV7180 video decoders. I will configure for a single ended output, as a CMOS clock signal on OUT[0:2], terminating the #OUT[0:3] by a 100nF to GND.
There are two questions related to my suggested implementation of the AD9508;
If dividing down my source oscillator clock by two, having a +/-25ppm frequency stability on the oscillator, could I expect a +/-50ppm on the output clocks out from the AD9508?
The analog video decoder shall have a 1.8V CMOS clock input. I am having challenge in sorting out the actual voltage swing from the AD9508 when using a single ended CMOS output. It is stated 2.5V to 3.3V power supply on the VDD pins, while reading 1.8V to 3.3V on the table 14 in the datasheet. Am I understanding the datasheet correctly when stating that I get a 1.8V CMOS output swing if using a 1.8V CMOS input clock source?