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ADSP-21489 external port DMA question

Question asked by marc_s1 on Feb 5, 2014
Latest reply on Mar 27, 2014 by Jithul_Janardhanan

I have connected an AD9248 ADC to the external port of the ADSP-21489 (pins ADDR4..ADDR20). PDAP_CLK is connected to pin ADDR2 and PDAP_HOLD is connected to pin ADDR3. PDAP_CLK is generated by the PCG module. The signal is present on pin ADDR2.

 

I have setup PDAP and DMA as follows:

  *pSYSCTL = PDAPFLAGS;  // PDAP through external port

 

  *pIIEP0 = (uint32)&data[0];
  *pIMEP0 = 1;
  *pICEP0 = data_count;

  *pIDP_PP_CTL = (IDP_P01_PDAPMASK  | IDP_P02_PDAPMASK |
                  IDP_P03_PDAPMASK  | IDP_P04_PDAPMASK |
                  IDP_P05_PDAPMASK  | IDP_P06_PDAPMASK |
                  IDP_P07_PDAPMASK  | IDP_P08_PDAPMASK |
                  IDP_P09_PDAPMASK  | IDP_P10_PDAPMASK |
                  IDP_P11_PDAPMASK  | IDP_P12_PDAPMASK |
                  IDP_P13_PDAPMASK  | IDP_P14_PDAPMASK |
                  IDP_P15_PDAPMASK  | IDP_P16_PDAPMASK |
                  IDP_P17_PDAPMASK  |

                  IDP_PDAP_PACKING3 | IDP_PDAP_CLKEDGE |
                  IDP_PP_SELECT     | IDP_PDAP_RESET    );

   
  *pPICR0 &= ~(0x1F << 15);
  *pPICR0 |=  (0x09 << 15);

  interrupt(SIG_P3, pdap_isr); //DMA ready interrupt
   
  *pDMAC0 = DEN | INTIRT; // enable DMA

 

The PCG is setup to generate a clock of 20 MHz. The time interval between starting DMA and the DMA ready interrupt corresponds with a clock of 50 MHz, so I get the impression that the 20 MHz PCG clock is not used to clock in data. What am I doing wrong?

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