Hello. I like to take the RFPLL in operation. Clock generation is enabled. The BBPLL is has locked. I have read the User Guide for this. On page 25 (AD9361 RF and BB PLL Synthesizer User Guide) there is an example to initialize the RF PLL. The RF PLL (Tx and RX) is not locked.
For example I tryed it like this:
(1) Clock generation enable -> (Reference clock at pin CLK_OUT)
(2) BBPLL locked
(3) RF PLL (TX)
- default for divider, ...
- set fractional word
- set integer word
- read tx lock bit out
First of all I like to test the pll without calibration of the charge pump, vco etc.
What could be the reason for that? Did I forget an important step in (3) ? Thanks