I'm wondering about the following:
I'm using the EZKIT21369. The SDRAM is configured like in the block-based talk trough example with a clock of 166MHz, DSP runs at 331MHz.
First I'm writing some test data to the SDRAM via core access.
Then I'm reading 8 blocks of 128 dwords via chained DMA. That is working fine so far. I can see the expected data in internal memory after
while( (*pDMAC0) & (CHS+DMAS) );
But now the strange thing:
If I limit the chain to only one TCB and do a cycle measurement I measure 395 cycles (for 128dwords). => transfer takes 1.2µs, right?
But that seems to long! I think it should be only 0.77µs (128/166MHz). Am I missing something here? Are there some extra steps executed when the DMA runs the first time? Or am I doing a wrong assumption in the calculation?