I have few questions about a/d d/a cores:
1)Why in cf_xcomm\system.vhd are there two instances each of adc and dac cores?
2) What SERDES mode is AD9122 DAC configured for nibble,byte, or word?
3) In cf_lib\edk_pcores\axi_ad9122_v6_00_a\hdl\verilog\axi_ad9122_if.v
why are there signals dac_data_i0,1,2,3 and dac_data_q0,1,2,3? These are 16 bit dacs? Total bits fed into serdes amounts to 64 bits?
4) Is it possible loop back adc into dac? This would be a nice test mode. I know it would require mods. Any guidance would be appreciated.
5) Can the DAC data rate be reduced to ADC data rate. If so how?