AnsweredAssumed Answered


Question asked by kcfarleysw on Feb 1, 2014
Latest reply on Feb 3, 2014 by rejeesh



FMCCOMMS1-EBZ FPGA Reference Designs: PCORE Register Map


1) What does the DAC_LB_ENB bit do?

2) Does it loopback the ADC to the DAC?

3) Where does the loopback occur. Before the DMAs and after the ADC/DAC interfaces?

4) Where is the verilog code at for this loop back?

5) Where is the software driver for this code?

6) I didn't see a way to set this bit in the web page. Is there a function to set this? How do you set this bit?


0x1105     0x4414     REG_CHAN_CNTRL_6     DAC Channel Control & Status (channel - 0)

        [1]     DAC_LB_ENB     RW     If set enables loopback of receive data (applicable only on shared interface).