1.What is the clock frequency of dac_div_clk of AD9122 core...?
2.What is the ratio between DAC actual sampling rate(i think default is 491.52Mhz) and dac_div_clk?
3.How can i set DAC actual sampling rate to 61.44Mhz?
It is best if you use either no-OS or linux to change the sampling frequency.
Otherwise, you need to go through the AD9523 register map, find the OUT pin the clocks connected to then program the OUT (divide) registers. If it doesn't get you the frequency you are looking for, you will have to go one level up to the VCO then change all the dividers.
The clocking specific to DAC is-
DAC_CLK = is the sampling clock used by the DAC.
DCI = DAC digital interface clock (DAC_CLK/interpolation) This is the dac_clk in your post above. But do not get confused by the sampling clock.
DAC_DIV_CLK = DCI/4 - always - if you haven't changed the design.
Are you using no-os or Linux?
The main clock is 983.04. if you want to get 61.44 MHz you need to divide the mail clock with 16.
I am using no-OS......
this makes dac_clk = 491.52 (983.04/2) and dac_div_clk = 122.88 (983.04/8)
m i rite?
so should i make changes here for clock division?
or should i change the clock division at AD9523 chip and all other clocks become appropriate? what register changes i have to do for it?
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