We noticed that the BF534 has a CLKBUF pin which is a clock output that is connected through a PLL and the CLKIN pin. We would like to use just a single 25MHz oscillator connected to the CLKIN and be able to use the PLL to get a 50MHz clock out on CLKBUF for the Ethernet PHY. But looking through the Embedded processor Rev G guide and the hardware reference manual it is not clear if the PLL for CLKBUF is tied to the PLL that we use for the SCLK. Ideally for what we are trying to do, it would be great if these PLL’s were separate so we can get both the 50MHz for the Ethernet PHY and the 125MHz for the SDRAM that we need. Would you be able to determine how this is setup internally?