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AXI Bus Bit width support

Question asked by jyi123 on Jan 28, 2014
Latest reply on Feb 2, 2014 by jyi123

We are using ML605 and FMCOMMS1 with NO-OS software and would like to make fully use of bandwidth between DDR and DAC via VDMA.

What's the AXI bus bit width for this design and what's the maxim data rate can be between DDR and DAC via VDMA?