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ADV7403 CP mode - HSync position

Question asked by WolfgangZ on Jan 28, 2014
Latest reply on Feb 3, 2014 by DerekBurke

We have an application with analog HD YPbPr input (720p, 1080i, 1080p) to the ADV7403 and tried to get a valid SDI YCbCr output signal over an FPGA.

we got the problem, the HSync of the digtal output of the ADV7403 is positioned nearly in the middle of the video signal in the default and example register settings.

We tried to shift the sync pulse modifying the registers 0x7b...0x7e but the range seemed to be too small.


Is there any undocumented register to shift the HSync to the correct begin of line?