I have been using an ADF4002 configured with R=1, N=1, 20 MHz signal with 1 ns pulse width driving RFinA and RFinB differentially with an LVPECL driver with an appropriate resistor network to reduce the differential swing to 500mV p-p, biased to approximately 1.6V and 50 ohm terminated at the pins. The signals looked perfect at the pins but I was not getting lock.
I placed the N-divider output on the MUXOUT pin and observed it generating large voltage spikes between the signal output pulses, enough to look like an edge to the PFD which explained why I was not achieving lock and the CP output was pulling low.
I placed a cap between the pins and adjusted the resistor network to give an ugly 250 mV p-p differential signal with a much slower edge which succeeded in reducing the output voltage spike and allowed the PLL to lock, but it looks like just barely.
I don't really know why this worked as I appeared to be meeting all the part specifications before, especially looking at the RF input stage basic schematic and running some SPICE simulations. Could it be the input duty cycle (which there doesn’t seem to be a specification for) ?
I am not really happy with this temporary solution as the signal at the ADF4002 pins looks poor as it is no longer properly terminated. I would like to change the input network to something robust that I will have confidence in, though all the variations I’ve tried that generate a clean signal at the RF pins do not achieve lock due to the voltage spikes.
Is there a recommended resistor/capacitor network for driving RFInA and RFInB from a LVPECL (or similar) driver (a posted example would be ideal)? Any ideas on the apparent N-divider output signal corruption? and is there any other RF input specifications I can follow?
1. ADF4002 has good supply decoupling close to the pins with no substantial supply noise observed.
2. The issue has been observed with 3 parts, so not an isolated case.