I am working with a BF518x and ran into a situation i didn't fully understand. I have an mdma transfer that occurs a dozen or so times a second. I expect an interrupt to occur once the transfer completes. Inside the interrupt handler, I read the corresponding SIC_ISR register one time when i enter the handler and check which SIC_ISR bit got me there. Then I check each peripheral under that sic bit to determine the source. Most transfers, lets say 99/100 transfer all data, hop into the appropriate interrupt handler and get processed exactly as I intend. The other times, the very first read of the SIC_ISR has no bits set, that correspond to the active interrupt vector. I did get the interrupt, to the correct handler, and if I check each peripheral and skip checking the SIC_ISR register everything works every time. I just want to understand why the SIC_ISR bit is getting cleared before i clear the status causing it.