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PCG SPORT

Question asked by DLi9 on Jan 27, 2014
Latest reply on Feb 11, 2014 by Jithul_Janardhanan

Hi,

 

I am currently using the block based talkthrough example for ADSP21369 clocked at CCLK of 332MHz. When I use the internal clock and frame sync for SPORT at max speed, everything works perfectly, however when I change to PCG (Following the programming model external input pin), the clock and frame sync has a delay half of the time and some how the data being transmitted has additional random values (usually very high but has no specific pattern). I was wondering if there was any reason for it. (the trasmit chain buffer uses the TCB rotational buffer copied from block based talkthrough

Code:

=========================SRU===========================

void SRU_init(void)

{

          // PCG connections

          SRU(LOW, PBEN20_I);

          SRU(DAI_PB20_O, PCG_EXTA_I);

 

          SRU(PCG_CLKA_O, SPORT1_CLK_I);

     SRU(PCG_FSA_O, SPORT1_FS_I);

 

     SRU (HIGH, PBEN19_I);

          SRU (PCG_CLKA_O, DAI_PB19_I);

 

          SRU (HIGH, PBEN17_I);

          SRU (PCG_FSA_O, DAI_PB17_I);

 

          // ADC data to SPORT1

          SRU (LOW, PBEN14_I);

          SRU (DAI_PB14_O, SPORT1_DA_I);

}

 

======================Register Config====================================================

void SPORT_PCGinit(void) {

     *pPCG_CTLA1 = 0;

     *pPCG_CTLA0 = 0;

 

          *pPCG_CTLA1 = CLKASOURCE | FSASOURCE;

          *pPCG_CTLA0 = BIT_8 | ENCLKA | ENFSA;

}

 

 

void SPORT_initSPORT1() {

          // Configure SPORT1 as Master output

          *pSPCTL1 = OPMODE | SPTRAN | SLEN24 | SPEN_A | SCHEN_A | SDEN_A;

}

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