I am using fast AGC mode on the AD9361. When a signal is received the receive gain changes rapidly and then remains fixed for a long period of time (~218 microseconds). During this time the AGC is unlocked and remains in AGC state 2. The AGC then enters state 3, lock status is asserted high, and the gain changes. These all occur simultaneously. It appears as though the AGC is performing one final long accumulation of the signal power estimate before setting the final gain. There is no mention of this behavior in the documentation. I would like it to lock the gain much faster. Is there a register configuration which is delaying the lock of the receive gain? I can provide more details if necessary.
A second question concerns the "Invert Bypassed LNA Polarity" bit, 0x022[D6]. With this bit set I do notice an improved phase balance between when the LNA is enabled and disabled. Is there any reason not to set this bit? Any negative consequences, performance degradation, etc.