I am using the AD9517 on two boards, and i am trying to synchronize all outputs such that the phase/timing between outputs on both board are repeatable at every power-up or reset cycle.
I have made all the necessary provisions:
1. External 10MHz reference to both AD9517 to be able to lock to the same reference.I have the external ref clock split into two and provided to each board.
2. AD9517 in PLL mode with an external VCO generating 1GHz clock output.
3. An FPGA on each board provides SYNC signal after the AD9517 indicates that lock is achieved. So i do not have 1 SYNC source that is split to the two AD9517.
I am having issues with getting the divided clock outputs on the two boards (250MHz clock, divided by 4 version of 1GHz) to come up with constant phase relationship at every power-up. At every power-up the FPGA on each board performs SPI Programming ==> LD status Check ==> SYNC ==> Done.
Is there any document that describes the desired sync procedure for multiple AD9517 ? Or, is there any problem with the setup i have described ?