what is the maximum current a GPIO can sink or source on the ADuC7020?
As described in the datasheet, five registers control each GPIO port: GPxCON, GPxDAT, GPxSET, GPxCLR and GPxPAR.
The GPxPAR MMR contains settings for drive strength and pull ups.
Medium drive strength (default)
Low drive strength
High drive strength
the two figures below respectively show the typical drive capability of a GPIO to sink and source current for the three configurations at low level and high level.
programmable strength for high level
programmable strength for low level
How do the drive strength control bits fit in to the existing GPxPAR MMRs, for the port pins that are configurable?
The Drive strength may be adjusted according to the attached tables.
You must make sure that the overall Idd drawn by all GPIO does not exceed 25mA. If this happens, the GPIO specs in the datasheet may not be met.
"..Note that the drive strength is only configurable on the following port pins: P0.7, P3[5-0]."
So there is an undocumented GP3PAR MMR? Is its address 0xF45C and default value 0x00000000?
Yes, but the MMR is already in the header-files.
Here the example from Keil MDK
My tests show a default value for GP3PAR @ 0xFFFFF45C of 0x00222222. i.e. low drive strength for pins P3.0 to P3.5 and medium drive strength for P3.6 & P3.7. Can you confirm this and also which pins on GP3 the pull-up control can be configured - is it P3.0 to P3.5 as the drive strength mentioned by AudeR?
The ADuC7023 says "The drive strength bits can be written one time only after reset". Is this the case for the ADuC7024?
I don't know if IAR have been informed, but my older EWARM 5.4 doesn't show GP3PAR in the GPIO AND SERIAL PORT debugger register window.
Hi. Thanks for the information.
Has that table (Table 56) you provided come from the current data sheet for a different device, or is it an extract from the proposed new revision data sheet for the ADuC702x (excluding ADuC7023), as intimated in http://ez.analog.com/thread/3995 by MMA, which will be produced at some future time?
Also, is the information on the timers presented in the data sheet for the ADuC7034 applicable to the ADuC702x - specifically the sections "SYNCHRONIZATION OF TIMERS ACROSS ASYNCHRONOUS CLOCK DOMAINS" & Starting & Halting Timer 2? (Obviously Timer 4 or the Lifetime function of Timer 0 is not present on the ADuC702x).
The tables included in the picture attached to the previous message came from an internal ADuC702x document and not from a different device datasheet.
As your second question, concerning synchronisation of timers on the ADuC702x, is a different topic to the original GPIO question posted on this thread, I will address it on a new thread: http://ez.analog.com/thread/4698
The tables appear to be the same as in the ADuC7023 Rev A data sheet - figure 37 and figure 38 on page 52.
This is correct, the ADuC7023 GPIOs structure is the same as that on other devices of the ADuC702x family.
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