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AD9910 SYNC_CLK Problem

Question asked by ami1pa1el on Jan 21, 2014
Latest reply on Jan 23, 2014 by LouijieC


I am using AD9910 for modulation purpose.I have got this evaluation board of AD9910.But I wanted full external control via FPGA which i was managed to get.In the start SYNC_CLK was perfectly coming as 1/4*F_SYSCLK.I was giving REF_CLK as 100MHZ and SYS_CLK should be 50MHZ and SYNC_CLK was coming 12.5MHZ and i was using SYNC_CLK to drive my fpga.I was running SPI at 500KHZ.And I was able to write to the registers of IC like 0x0E (Profile 0 for Tone) and was getting tone at required frequency.

But then next day when i started board I was getting SYNC_CLK as 50MHZ still i changed some PLL setting in FPGA and tried to write in registers in IC via SPI but this time I was not and i was getting any tone in output.

It would be great if you could demystify this.