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ADV7441A - HDMI CP Bypass mode

Question asked by Chuckrlee Employee on Jan 21, 2014
Latest reply on Jan 21, 2014 by PaulS

We’ve implemented a solution using this CP Bypass mode that seems to be pretty reliable, but our software team has identified one strange thing: Whenever CP Bypass mode is enabled, the STDI valid interrupts seem to go haywire, which causes the driver to be frequently interrupted and slows performance. They’ve implemented a mechanism to deal with the instability, but it’s not ideal.

 

My first question is the following: Why would the STDI interrupt keep firing if the input resolution is stable and CP Bypass mode is enabled…? It is my understanding that the STDI block identifies those resolutions that it recognizes and asserts the interrupt when a known resolution is detected. In this case, the resolution is unknown, but stable…

 

My second question is of a more general nature: It appears that in CP Bypass mode the input TMDS signals are simply decoded and sent to the ADV7441A’s outputs, implying that there is no guaranteed timing relationship between the syncs, pixel clock (or line-locked clock, as you refer to it) and data, whereas in CP mode the chip ensures that a proper timing relationship exists between the pixel clock and output data (as well as permitting the re-timing of the H- and V-syncs)… Is this understanding correct?

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