Some question about non-standard I2C read sequence with ADuC7023 in slave mode:
According to the I2C standard, the master terminates multiple reads sequence by NACK-ing the last byte, then STOP:
However, there are some non-standard masters, where master ACK even the last byte, then STOP.
When slave get the ACK, it start to send the next byte. If next byte start with HIGH bit,
everything OK, since the master force SDA to LOW, then performs STOP.
However, the problem arise if the next byte start with LOW bit, master can't release SDA to HIGH during STOP sequence, and STOP is discarded, and master is stalled:
My customer has such masters in his system, and he says that other providers success to interface with his masters without problems.
How could I interface with those non standard masters?
Is there any HW/SW trick that will do the job?