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Clarification on the Evaluation board of AD9914

Question asked by Durgesh.R on Jan 18, 2014
Latest reply on Jan 24, 2014 by sitti

Hi !

 

In the Evaluation Board ADCLK925BCPZ-WP is used to drive the DDS Clock.I checked the data sheet of ADCLK925BCPZ-WP. In Phase noise plot of Data Buffer Some spurious are there . Will it create problem in the Jitter ? . If yes Suggest me the best method of Driving the DDS with 3.5GHz Clock.

 

Thanks,

 

Durgesh.R

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