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AD1974 PLL sometimes does not lock on power up

Question asked by Lionelwallace Employee on Jan 16, 2014
Latest reply on Feb 12, 2014 by DaveThib

This is from a customer:


Initial comments:


The AD1974 is the main ADC that we are using and from day one (almost two years ago) these ADCs have had the issue that their internal PLL does not always come up and lock. It usually will, but when it does not, I would just reset it. But for the past few days I have been trying to make these come up every single time no matter what and I cannot seem to get them to always come up. I have tried all sorts of delays between resetting, sending commands, etc… even extreme delays of several seconds.


Folllow up comments:


Attached is the schematics for the ADC section of our design. I should point out that our system is modular and there are two AD1974 per card, with up to 4 cards per chassis. The MCLK is one of two different clocks (22.5792Mhz or 24.576Mhz which run through a clock fan-out buffer so that each card has its own MCLK (each pair of AD1974 share a MCLK feed). The AD1974s are always slaves. The sample rates change between 44.1kHz, 48kHz, 88.2kHz, 96kHz, 176.4kHz, and 192kHz.


Once the ADCs are up and running, they work great and continue to work without losing lock on the PLL. It is when changing between samples rates that they sometimes fail to lock (At least I am suspecting that they are failing to lock because my output audio has about 10% distortion on it no matter what amplitude the input audio is.  I did not have the SPI data out pin connected so I currently do not have a way to read the registers on the AD1974 to see if the PLL lock bit is set or not. I am about to connect to this data out pin and read that register to see if this is really the case. But I can tell you that when it “fails to lock”, I can simply reset the ADC and send the same registers (Really I am only changing two registers from the defaults… I set the Clock Control 0 register to 0x9C which sets the input to the PLL to MCLK, disables the XTAL out, sets a 512 clock rate, and powers up the PLL… I also set the ADC CTL0 registers to either 0x00 for 44.1/48kHz, 0x40 for 88.2k/96k, and 0x80 for 176.4k/192k) and it will come up and work with about 0.003% distortion instead of 10% distortion. I figured it was just that the clocks were not stable for the PLL, so I put delay after changing the clocks before I reset the AD1974s and brought them on. Like I said, it is just like once every 10th time or so that I change sample rates that it does this but I need for it to always lock before we can release our product. Any suggestions?


Any ideas?