AnsweredAssumed Answered

Reloading the PCG

Question asked by Raymond on Jul 3, 2010
Latest reply on Jul 13, 2010 by Raymond



I have an ADSP-21469 EZ-kit and I'm using the PCG with an external clock input to drive the bit and world clock inputs of both SPORT1 and SPORT2. These in turn feed audio output to the DAC.


Configuring the PCG works as expected and I can output the correct clocks for a specific sample rate (say, 44.1Khz).

However, when I reconfigure the PCG for a different sample rate, it continues to output at the same rate although the configuration registers have been set correctly for the new sample rate....


The method I use for reconfiguring the PCG:


int pcgWait = 0xFFFFFFF; // Ridiculously long for testing purposes


void setOutputSampleRate(unsigned int sample_rate, int precision, int channels)  {
     unsigned int div = PCG_SRC_FREQ/sample_rate;
     unsigned int clockdiv = (PCG_SRC_FREQ / (sample_rate * precision * channels));
     //Avoid reconfiguration if not necessary
     if(currentSampleRate == sample_rate) {
     //Store the new sample rate.
     currentSampleRate = sample_rate;
     //Disable PCG
     *pPCG_CTLA0 &= ~(ENCLKA | ENFSA);
     //Reset frame sync, phase and clock to 0
     //Load new frame sync and phase, phase equals framesync to have framesync
     //and clock in sync (so no leading or tailing clock)
     *pPCG_CTLA0 |= (FSAPHASE_HI & (div << 10)) | (div);
     //Load clock.
     *pPCG_CTLA1 |=     (FSAPHASE_LO & (div << 20)) | (CLKADIV & clockdiv);
     //Wait before enabling, executes pcgWait 'nop' instructions.
     //Enable clock
     *pPCG_CTLA0 |= (ENCLKA | ENFSA);


Am I missing something? Is there anything else that needs resetting when the PCG is reloaded?


Any help would be much appreciated.