First of all. I not an expert and just started playing with FPGA...
In my application, I designed a signal filter for real-time pulse shaping. It seems that this filter can run at a maximum frequency of 100 MHz.
However, I don't currently have a 100 MHz clock to drive the AD9467 card.
Right now, I have enabled the onboard oscillator so the AD9467 is running at 250 MHz.
Using the reference design that AD provided and a clock manager in xilinx EDK, I am able to get a working design. The output from the adc pcore in xilinx EDK is pumping out data (adc_mon_data) at 250 MHz (adc_clk). I use this clock (adc_clk) to drive a mmcm and output a 100 MHz clock to drive my design. It seems to work, but there's some spikes in the acquired waveform which I suspect is a result of the unmatched clock.
How can I utilize the AD9517 onboard? I read ug-200.
Should I choose the LVDS clock option? Basically, install C306, C307 and remove C209 and C210? ( I have already installed C206 and C205, removed C202). If I set P200 to ON, I should be good to go? Will the AD9517 driver provided in the reference design allow me to set the ADC clock frequency to 100 MHz?