We are setting AD9253 to test mode, by writing the register 0X0D as "0x08".
We are feeding some user data into the registers, and we try to read these data back inside the FPGA, by taking DCO clock as reference. We have kept the Output clock Phase adjust value to Default (180). But we are seeing inside FPGA that, for every frame, we are getting different datas.
Only after we set the Phase adjust to 660 degree, we are getting consistent data for all frames. But even then, the data is not same as the data we are feeding. When we fed (F6F6), we are getting (1BD3) and when we fed (ABCD), we are getting (2AF3) inside FPGA. Why are these variations?
We have length matched, clock and output data lines. So the default phase value should be the correct one, isnt'it?