We haven't implemented watchdog hardware the way it was implemented on the evaluation board. On our board, WDTRSTO is not connected to anything. On the eval board it is connected to a reset chip. Is that the problem? Is there eratta on this 21489 related to this?
1. When our Watchdog timer trips, it just holds processor reset low. If I look at RESETOUT pin on the processor, it stays low (asserted) after the watchdog timer trips. In our code (below) we said that we allow the watchdog to trip 7 times before holding the processor in a reset state, so this is a bit confusing.
Watchdog initialization code is below:
*pWDTUNLOCK = 0xAD21AD21; // Before writing to the WDT configuration space, UNLOCK WDT by writing the command value 0xAD21AD21
*pWDTCLKSEL = WDT_CLK_SRC_CER_RESO; // Selects an external clock (0x0000000)
*pWDTTRIP = 0x7; // number of times that the WDT can expire before /WDTRSTO pin is continually asserted until the next time hardware reset is applied
*pWDTCNT = 0x3FFFFF; // 32-bit unsigned count value - 2MHz external clock ---> T=500ns
// 0x3FFFFF = (d)4194303
// 500ns * 4194303 = 2.09 sec
// Wait before enable Watchdog timer
// WDT effect latency - 2.5 WDTCLK cycles at 2 MHz
for(n = 0; n < 50000; n++ ) //**** Was 500
*pWDTCTL = WDT_EN; // Enable the Watchdog timer
*pWDTUNLOCK = 0; // After configuring the WDT registers, the core needs to LOCK it again by writing any value other than the command value
2. A few more details on this Watchdog thing.
The first detail is, when we are seeing this reset phenomenon, not only is Processor Reset Out continuously low, but also WDTRSTO is also continuously low.
The second detail is that we are feeding the watchdog with a timer output. So when the processor is reset, the timer stops.
Does the watchdog timer require a continuous external clock in order to de-assert reset after the watchdog timer trips?
Please let me know your ideas on this .