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Data Latency(Pipeline Delay) Explanation for AD9910 DDS

Question asked by TIBO on Jun 30, 2010
Latest reply on Jun 30, 2010 by TIBO

We have been used AD9910 in our systems. I need to explanation of data latency detaily. For example what does below specs mean, given in the AD9910 datasheet;

Data Latency, Sweep Mode

Frequency, Phase-to-DAC Output           Matched latency enabled/disabled           91 SYSCLK cycles

Amplitude-to-DAC Output                       Matched latency enabled                        91 SYSCLK cycles

                                                                                Matched latency disabled                       47 SYSCLK cycles


I have used frequency sweep function from DRG module of AD9910. Also, at the same time I want to change phase of the signal from RAM module.

For example, DRG sweeps the frequency from 200-210MHz with 1MHz delta frequncy and 16ns dwell time (DDS REF CLK = 1GHZ); that is there is total 11 frequency from 200MHz to 210MHz. In addition, RAM module has some phase information such that there is a unique phase word for each frequency that is RAM has also 11 different phase word. Finally, while DRG sweeps frequency with 16 ns dwell time, RAM also sweeps(changes) phase with 16ns dwell time; that is when DRG sweep from one frequency to another, RAM should also changes phase from one to other. So, Do these frequency and phase changes simultaneously or not? As the datasheet gives the latency time 91 sysclk for frequency,phase to DAC output, does that mean simultaneus frequency and phase changes occur after 91 sysclk delay? If it is, what does DDS output do while waiting 91 sysclk delay?

Thanks for your consideraitons.