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ADV7181 output timing

Question asked by CRU on Jan 13, 2014
Latest reply on Jan 13, 2014 by GuenterL

Hi,

 

The ADV7181 is currently configured in DDR 4:4:4 and is generating a pixel clock of 108Mhz.

It's connected to a fpga and i'm trying to write timing contraints on the inputs.

I'm using t15 to t18 characteristics and the values are :

 

t15 = -1.69 ns

t16 = 2.56 ns

t17 = - 0.64 ns

t18 = 1.81 ns

 

you can find a short description in attached file.

 

The problem is that timings on the edges are quite differents. The common timing area is just 120 ps (1.81-1.69).

In my point a view, the only manner to respect timings is to use an internal PLL to compensate.

Either with two output clocks (each dedicated to an edge) or one output clock with a duty cycle of 61%.

 

Do you agree with that ?

 

Regards.

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