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24kHz sampling on ADAU1442 - achieving the highest core clock

Question asked by IanH on Jul 2, 2010
Latest reply on Jul 6, 2010 by JeradL

My application has all sampling at 24kS/s and the ADAU1442 is the clock master.


What is the best way to set up the ADAU1442 crystal, clocking and PLL to maximise the processing cycles available for my application with 24kHz sampling?


At 48kHz normal rate, 3584 instructions can be achieved per sampling instance.

Can 7168 instructions be achieved at this 24kHz "half-rate" sampling?


I also want a synchronised clock out to feed to my FPGA so that other digital audio processing can be achieved. This should be the highest rate possible. What frequency can be achieved and how would I set it up?


Thanks in advance.