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Capturing XGA (1024x768@70Hz) with SOG using ADV7403

Question asked by IanC on Jan 10, 2014
Latest reply on Jan 13, 2014 by IanC

We are capturing 1024x768 (70Hz) RGB video, with sync on green using the Evaluation board.


I am set up with


VID_STD=0xD (1101)

Free run line length -= 0x1FB (507)

TLLC Control Analogue [ SOG_SYNC_LEV] = 0x1B


CPOP_SEL = 0 or 2


The STDI info shows the video locked and the correct clock counts for the video mode.


Looking at the digital data output I can see the video data is following the incoming video blanking timing (with a slight delay).


However, the hsync generated by the chip is shifted half way into the video line. When I use the sync for display I end up with the shifted/wrapped display.


I've used the CP HVF CONTROL register to try moving the HS start/end but I can't move it far enough to fall int he proper HSYNC period.


Why is the HS appearing half way into the line ( a delay of 10+ us) but the video is not shifted by the same pipeline delay?


How can I get the HS to follow the input directly ? (Or conversely why is it not doing so?)


Appreciate any help, I can provide more information if needed.