Hello, I am developing a product that uses the ADV7401 as a decoder an ADV74343 as the encoder. I have developed a simple test design and to have something to compare to had Kevin Laird AD FAE sent me a reference design: Eval_ADV734xEBZ_revC_Jan08.pdf yesterday.
Looking at the ref design, nearly identical to what I have put together myself, so that's good One question though, on Page 3 of the eval design, the 7401/3 chip...the pixel bus outputs s0...s9, y0...y9, c0...c9 seem to be backward LSB to MSB, on the 734x the bit ordering is LSB to MSB s0...s7 for
example, but this designer has them in backward order from the bus P29..P20..
Unless there is an invert bit order register that I missed? This flips the order of the pixel port bits and that's what he is relying on? Referring to the ADV7401 data sheet page 221 ish shows all the pixel port configurations and they are all in MSB to LSB descending order, so seems this design has the bits backwards?
In essence, does the designer of the ref design have all the bits backwards on his pixel output/input buses?
I have attached an image of the confusing buses, seems they should be MSB to LSB top to bottom.
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