I want to extend the 7850 SDK to handle additional analog formats in Autographics mode. Is there a method of determining the correct values for de_h_start, de_h_end, de_v_start, and de_v_end?
You should get them from the CEA 861 standard. If the format isn't in there, you'd need to figure it out yourself as there is probably not a DE defined. DE is simply active during active pixels though so it shouldn't be hard.
I'm having some difficulty correlating the de_h_start and de_h_end adjustments to the standard. For instance, the 7850 SDK autographics mode settings for 1360x768 @ 60 Hz are 0x01C (28) for de_h_start and 0x3F8 (-8) for de_h_end. How are these values derived from the timing standard?
As far as I can tell that is not a standard in CEA861F so DE is not defined. The values were either determined experimentally from a source or picked from whatever standard they had for it.
de_h_start should be the first pixel on a line that is active. de_h_end should be the last, for example.
Maybe 1920x1080p @ 59.94 Hz is a better example since it is not supported in the 7850 SDK and is a CEA standard. Can you tell me what the appropriate de_h_start and de_h_end register settings would be for this format?
Thank you for your help,
For a CEA standard, if you look at the General Progressive Video Timing you'll see the definition of DE per line is that it goes active at pixel [Hsync + Hback] and ends after Hactive pixels. Those values are specified per standard in tables in section 4.
The problem I am having is with translating the DE start and end positions from any given timing spec to the appropriate de_h_start and de_h_end registers on the 7850 which appear to be signed offsets to some unknown (to me) default. For instance, the spec for 1920x1080p @ 59.94 Hz specifies an H Front Porch of 88 pixels,an H Sync Time of 44 pixels, and an H Back Porch of 148 pixels. How do I get from these fixed values to the neccessary offsets in the 7850?
HDMI does not directly transmit DE signals like H & V sync signals which are part of channel 0. DE is transmitted by how the video data and sync data is encoded. Therefore at the receiving end the DE is created by interpreting the encoding format. So the bottom line is the received DE is whatever the source sends it. (check out the encoding algorithm in the DVI 1.0 standard, it's got the easiest to understand description of this in my opinion.)
The registers you mentioned above, when zero introduce no shift in the DE signal edges. They will allow you to move the edges based on pixel clocks and the original received DE. This is what the 7850 uses.
There are ways to move the VS edges like register start_vs and end_vs but theses only move the edges by +-8 lines. Generally you do not have to do this either since the source will generate the correct VS and HS signals.
Our current need is to extend the ADV7850 SDK's video lookup tables to support additional analog only signals (we are not using HDMI In for this application) in autographics mode. If possible, we would like to avoid having to manually tune the de_h_start and de_h_end register settings. Or, at least be able to calculate values that might approximate the optimum solution as a starting point for final tuning. It seems to me that these values should be determinant in some manner from the timing standard but I haven't had success in figuring it out. Ultimately, what I think I need to know is what the H front porch, H sync width, and H back porch will default to for a given timing format.
If it's not defined in the VESA standards then you will have to generate you own front sync counts for the format. Continued off-line
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