We are using an display with an ILI9341 controller connected to a BF609. We need to use the parallel micro controller interface for speed reasons. We want to transmit the image using DMA. There, we encountered the problem that we need generate a EPPI-CLK signal very exactly, i.e. only clocking out when the DMA is actually transferring image data. Otherwise, the controller will clock in additional unwanted pixels.
1) We found no way to synchronize the EPPICLK signal exactly, i.e. turning on with the first data byte and turning off with the last data byte. Is there a way to do that?
2) An alternative is to use the Chip Enable of the display to gate what data is transferred. Here the signal has to be low only while data is transferred by the DMA and high after the last data word (pixel) until the clock is turned off. We could use the FS1 signal as chip enable in general purpose 1 (GP1FS) mode. Is there a more detailed description of the timing and signals than the hardware reference manual? A few diagrams would be helpful...