I would like to configure the ADF4350 for a clock of 1600 Mhz with the lower phase noise possible.Could anybody help with the register configuration most appropiate?
If your ADF4350 output is fixed at 1600 MHz, then you can use a very narrow loop bandwidth to minimize the phase noise. You should also use the highest PFD frequency possible - the maximum on the ADF4350 is 32 MHz, so you would need a 32 MHz or 16 MHz reference source.
ADIsimPLL will help you design your loop filter and run simulations showing you the phase noise. Free download and instructional video here: www.analog.com/adisimpll
You should also set the ADF4350 in low noise mode. See Low Noise and Low Spur Mode in the data sheet: http://www.analog.com/static/imported-files/data_sheets/ADF4350.pdf#page=18
I tried also to use the ADF4351 at 1600 Mhz. Configuring the ADF4351 with the same configurations of the ADF4350 I am obtaining the same behavior, however, activating the Phase Adjust option (only present in the ADF4351) we are not obtaining the correct final frequency of 1600Mhz
Is there any limitation related with this option?
This is expected. The ADF4350 and ADF4351 VCOs are made up of several frequency bands (see figure below). Every time you write to R0, i.e. set a frequency, there is a band select process to choose the correct frequency band for your desired frequency. When you enable Phase Adjust, the band select process is disabled; so, if you're not already in the correct frequency band, then the part won't be able to output the correct frequency.
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