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AD9361 REF_CLK Level

Question asked by Bill.Englemann Employee on Jan 8, 2014
Latest reply on Jan 17, 2017 by ggozdemir


On page  5 of RevD data sheet, the typical level of REF_CLK is specified as 1.3Vpp, no Min and Max numbers are given.

On page  3 of “AD9361 Reference Clock Requirements” document, the level of REF_CLK is suggested as 1.3Vpp Max.

Could you help us find out the Min and Max level range requirement of this reference clock? Can it take 3.3V LVCMOS input? Is we have the option to provide 0.8Vpp clipped Sinewave and 3.3V LVCMOS clocks, which is better for the performance?

Thank you.