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Positive Gain Error correction in AD7734

Question asked by jebaspaul on Jan 7, 2014
Latest reply on Jan 16, 2014 by jebaspaul



I need some clarifications with respect to the information given in the data-sheet of AD7734. It is mentioned that the positive gain error is 0.5% of FSR. It can be translated to 50mV if the full scale rating is 10V. In the datasheet this parameter is hyper-linked to the note 3 given under table 1. In note 3 it is mentioned that "specifications before calibration. Channel system calibration reduces these errors to the order of the noise".


Can I assume that using system calibration mode along with a precise +10V input, this ADC is able to reduce the Positive gain error to an extend of <0.01%.