What is the expected latency of L2 comparing to L1 data.
is there a way to reduce latency?
If you are using BF548 processor, you can refer Chip Bus Hierarchy chapter in the processor's HRM. The On-Chip L2 Interface section provide details about access time & latencies involved in various L2 accesses.
Unfortuantely, I am not aware of any ways to reduce these latencies. Someone having understanding of it, may be able to offer some suggestions.
I have moved this from the Processors and DSP community to the Blackfin Processors community. Please continue the discussion here.
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