I want to create an optimally small footprint solution in HDL that will give me the ability to send a low sample rate data stream to the DAC on the FMCOMMS1 board and periodically grab snapshots from the onboard ADC (also at a low rate) centered on the TX output and roughly the same bandwidth. I'm hoping that by choosing a lower fdata I can make some simplifications in the interfaces. The data source is a custom modulation done in VHDL which produces a complex baseband data stream. By adjusting the clock rate to the module and the data valid of the input I can set it up to produce any data rate needed to make this as easy as possible. Basically I just want to see a display on a spectrum analyzer showing that the output of this module is being transmitted over the air. Bandwidth, center frequencies etc can all be set to whatever is needed to simplify the task. I assume since I am producing complex baseband (DC center), the TX output will be at fdata/2. But I will wait on your answer. Any suggestions?