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AD9434 difficulties

Question asked by frankd on Jan 6, 2014
Latest reply on Jun 1, 2017 by ljs

Hello ADI support:

I am using the AD9434 ADC in a chemistry measurement system.  The AD9434 output is LVDS into Altera FPGA, but FPGA side is non-terminated (See Schematic Page 13 below).

SiTime Oscillator SiT9107AC-23FH33E500.000000 drives AD9513, strapped for 1:1 for driving AD9434 Clock. (Page 9)

These lines 100 ohm differential pairs are terminated on-board in 100 ohms (See Page 25)

 

We have tested the output for fixed pattern transmission by setting Test_IO Reg 0Dh Bits7 & 6 (with fixed patterns loaded into Registers 19h,1Ah, 1Bh, 1Ch) and have no errors receiving

USER_PATT1_LSB,USER_PATT1_MSB

USER_PATT2_LSB, USER_PATT2_MSB

 

When we clear the bits in Test_IO Reg 0Dh  for analog ADC output, we get this pattern with a DC voltage in or a sinusoidal input:

 

scopeplot.jpg

Page13:

page 13.jpg

 

Page 9:

Page 9.jpg

 

Page 25:

page 25.jpg

Can you help me resolve this issue? 

Let me know if you require more info.

Thank you

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