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FMCOMMS2 Zedboard no-OS Chipscope ADC signal not as in demo

Question asked by DanMa on Jan 7, 2014
Latest reply on Jun 17, 2014 by DragosB

Dear,

 

We have some issue to get the demo running as showed.

 

We are using the HDL reference ad_fmcomms2_ebz_edk_14_4_2013_10_22.zip and the latest no_OS-master 1223 version from github

We generated the bit file and we get two errors when we compile the code.

Basically we solved this in changing xparameters.h :

comment

// CF_AD9361_RX_DMA_BASEADDR           XPAR_AXI_DMAC_0_BASEADDR

// CF_AD9361_TX_DMA_BASEADDR           XPAR_AXI_DMAC_1_BASEADDR

replaced with

CF_AD9361_RX_DMA_BASEADDR           XPAR_AXI_VDMA_1_BASEADDR

CF_AD9361_TX_DMA_BASEADDR            XPAR_AXI_DMA_1_BASEADDR

 

Then we used Chipscope to verify that all works. The DDS works ( see probe_tx_data ), but not the Rx ADCs signals ( see probe_rx_data )

 

1. Are this base addresses  re definition expected ?

2. Any idea why ADC part is not working  ?

 

We tried to investigate further in looking at the verilog code axi_ad9361_v1_00_a\hdl\verilog and we don't understand the why the output signal alternate between i2[5:0] and i2[11:6].

  4'b1011: begin
    tx_frame <= 1'b0;
    tx_data_p <= tx_data_i2_d[ 5:0];
    tx_data_n <= tx_data_q2_d[ 5:0];
  end
  4'b1010: begin
    tx_frame <= 1'b0;
    tx_data_p <= tx_data_i2_d[11:6];
    tx_data_n <= tx_data_q2_d[11:6];
  end
  4'b1001: begin
    tx_frame <= 1'b1;
    tx_data_p <= tx_data_i1_d[ 5:0];
    tx_data_n <= tx_data_q1_d[ 5:0];
  end
  4'b1000: begin
    tx_frame <= 1'b1;
    tx_data_p <= tx_data_i1_d[11:6];
    tx_data_n <= tx_data_q1_d[11:6];
  end

 

3. Is this the root cause of the ADC signal looking weird ?

 

Regards,

Dan

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