We are currently designing using AD9518-1 and two AD9739 as multiple synchronization, interleaving ADCLK944 as clock buffer in order to compensate the width of output voltage swing from AD9518-1. Could you please provide advices or check whether the circuit scheme shown in below is good or not ?
Particular points we are concerning are,
a) Input for ADCLK944 is dc-coupled, however is it not need to be ac-coupled ?
b) In regard to line between ADCLK944 and AD9739 DACCLK, are these parameters adequate at output impedance 200 Ohm, differential line impedance 100 Ohm, and input impedance 100 Ohm ?
c) Please advise on layout of PCB pattern I attached.