The PFD (phase frequency detector) can be difficult to understand. Ideally, the PFD output is a linear function of the difference in phase and frequency between the reference input and the divided down VCO frequency. In reality, the PFD typically has a linear range going both positive and negative, but often with a flat dead zone in the middle as the phase and frequency difference cross zero. If the PLL is in the locked state, the PFD out is constantly transitioning around this dead zone. The result of this non linear activity can cause spurs in the synthesizer output. The phase offset control is a small offset that is applied to the charge pump that follows the PFD. Although it is called a phase offset in the 6702 datasheet, it's referred to as bleed current in more recent devices, this is a more accurate definition of what is actually happening. The effect of this is to move the transfer function of the PLL positive or negative, so that in the locked state, the spurs caused by the PFD nonlinearity are minimized.
I know this may not be easy to understand, please let me know if this is not clear or if you have more questions,
My apologies, but could you please repeat this question in English?
This phase offset can be either positive or negative depending on the value of DB17 in Register 4, positive offset isn't easier to lock, but negative offset is normal, I want to know difference between positive offset and negative offset, and detail meaning.
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