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AD1933 DAC generate undesired signal

Question asked by sum on Jan 3, 2014
Latest reply on Jan 8, 2014 by DaveThib

Hi,

 

I drive a AD1933 in slave mode. The digital input of DAC is connected directly to FPGA. The AD1933 runs in TDM - Mode.

The AD1933 becomes MCLK (Master Clock: 12,288MHz), BCLK (Bit Clock: 12,288MHz) and DACLRCLK (DAC LEFT RIGHT Clock: 48 kHz) from FPGA design and also 24 bit pcm audio. So, i transmit four stereo channels (eight sub channels) to this device. Everything works fine up to this time. When i disable the audio output on FPGA side then it generate a 243 kHz sinus wave on his output channels. When i mute all output channels of DAC over the SPI interface, it does not change nothing on output. When i generate a 1 kHz sinus wave, then the output signal is overlay with 243 kHz undesired signal.

Why it generate a 234 kHz sinus wave on his output when it does not receive any data?

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