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Vivado 2013.2 - Clock constraints for AD-FMCOMMS1-EBZ reference design

Question asked by elvisjohndowson on Dec 27, 2013
Latest reply on Jan 16, 2014 by rejeesh


I'm getting intra-clock path timing errors after adding a ILA v2.0 probe to monitor the ADC debug ports, using Vivado-2013.2, for the ZC702 and AD-FMCOMMS1-EBZ reference designs.



Here is a screen-shot of the post-implementation timing report:



The original clock constraints were as follows:

# clock constraints

# clocks


create_clock -name ps7_fclk0    -period 10.00 [get_pins system_i/processing_system7_0/FCLK_CLK0]

create_clock -name ps7_fclk1    -period  5.00 [get_pins system_i/processing_system7_0/FCLK_CLK1]

create_clock -name ps7_fclk2    -period  8.00 [get_pins system_i/processing_system7_0/FCLK_CLK2]

create_clock -name hdmi_clk     -period  6.73 [get_nets system_i/axi_clkgen_0/inst/i_mmcm_drp/mmcm_clk_0_s]

create_clock -name dac_div_clk  -period  8.64 [get_nets system_i/axi_ad9122_0/inst/i_if/i_serdes_clk/i_mmcm_drp/mmcm_clk_1_s]


create_clock -name dac_clk -period 2.16 [get_ports dac_clk_in_p]

create_clock -name adc_clk -period 3.85 [get_ports adc_clk_in_p]


# timing exceptions


set_false_path -from [get_clocks ps7_fclk0] -to [get_clocks adc_clk]

set_false_path -from [get_clocks ps7_fclk2] -to [get_clocks adc_clk]

set_false_path -from [get_clocks adc_clk] -to [get_clocks ps7_fclk0]

set_false_path -from [get_clocks adc_clk] -to [get_clocks ps7_fclk2]


set_false_path -from [get_clocks ps7_fclk0] -to [get_clocks dac_div_clk]

set_false_path -from [get_clocks ps7_fclk2] -to [get_clocks dac_div_clk]

set_false_path -from [get_clocks dac_div_clk] -to [get_clocks ps7_fclk0]

set_false_path -from [get_clocks dac_div_clk] -to [get_clocks ps7_fclk2]


set_false_path -from [get_clocks ps7_fclk0] -to [get_clocks hdmi_clk]

set_false_path -from [get_clocks hdmi_clk] -to [get_clocks ps7_fclk0]


set_false_path -from [get_clocks ps7_fclk0] -to [get_clocks ps7_fclk2]

set_false_path -from [get_clocks ps7_fclk2] -to [get_clocks ps7_fclk0]


I managed to get the implementation to complete by temporarily ignoring the clock constraints:

# timing exceptions


set_false_path -from [get_clocks ps7_fclk0]

set_false_path -from [get_clocks ps7_fclk2]

set_false_path -from [get_clocks adc_clk]

set_false_path -from [get_clocks adc_clk]

set_false_path -from [get_clocks dac_div_clk]

set_false_path -from [get_clocks hdmi_clk]


and was able to get an approximation of the IQ outputs using Vivado Analyzer, as shown in the attached diagram:



However, I'd like to revisit the clock constraints and try to learn why the applied constraints are different from the figures mentioned in the functional overview wiki page


I have a few questions:


Q01: In the AD-FMCOMMS1-EBZ reference design, is the FMC board being clocked by the on-board 50 MHz oscillator, or by the FPGA through the FMC connector at 30 MHz?


Q02: In the xdc constraints file, the adc_clock period is defined as 3.85 ns, which roughly corresponds to 259.74 MHz

create_clock -name adc_clk -period 3.85 [get_ports adc_clk_in_p]


but according to the board's functional description in the wiki page, it states that the AD9523 takes the input reference clock at generates a 245.76 MHz clock for the ADC sample rate.



Key components:

AD9548 Quad/Octal Input Network Clock Generator/Synchronizer  (1Hz to 750MHz).
AD9523-1 Low Jitter Clock Generator (1MHz to 1GHz) with 14 Outputs.


The system may be clocked either through the on board crystal (50MHz) or from the FPGA (through FMC). The clock path mainly consists of an AD9548, AD9523-1 and two ADF4351 for the transmit and receive LOs. When using multiple boards with external synchronization, the slave boards must use the clocks from the master board.

The AD9548 has it's REFA inputs (in the schematic 9548_REF_[PN] nets) tied to the FMC connector's LA_17_[PN]_CC pin. This allows the clock from the FPGA to provide a clock to the AD9548, which then is cleaned up (jitter is removed), and driven out on OUT0[PN] to the AD9523-1 in REFB. The AD9523 then upconverts this signal to ~3GHz, and then divides this back down to any integer dividor of this ~3GHz output.

The default reference design that ADI provides does the following:

  • FPGA generates a fixed clock frequency of 30MHz using Xilinx clock generator.

  • This 30MHz is transmitted to the AD9548.

  • This is cleaned up (from a jitter standpoint) and sent to the AD9523.

  • The AD9523 takes this, and creates:

    • 491.52 MHz for the DAC sample rate

    • 245.76 MHz for the ADC sample rate

    • 122.88 MHz for the reference clocks for the LO PLLs.

These clocks can be changed, but the key thing to remember is that the AD9523 drives both the ADC and DAC. The AD9523 has two clock banks (see figure 1 in the datasheet), Bank 0: 0-3 & 10-13, and Bank 1: 4-9. The outputs on the different banks need to be integer mutliples of eachother. The best thing to do if you are interested in the details of this, is to get the Eval board software, and play with the different settings (you don't need a demo board connected to run the software).


Is this an incorrectly defined constraint?


Should the clock timing constraint be 4.06 ns (245.76 MHz) rather than 3.85 ns (259.74 MHz) in the xdc file?




Elvis Dowson